Transistors with dielectric-isolated source and drain regions

ABSTRACT

Semiconductor devices include a semiconductor layer comprising a channel region and source/drain regions. A gate stack is formed on the channel region. A dielectric layer is formed on the semiconductor layer in the source/drain regions. Source/drain structures are formed over the dielectric layer in the source/drain regions.

BACKGROUND Technical Field

The present invention generally relates to transistor design andfabrication and, in particular, to transistors having dielectricisolation of source/drain regions on bulk-semiconductor substrates.

Description of the Related Art

Field effect transistors (FETs) can be formed on bothsemiconductor-on-insulator (SOI) and bulk-semiconductor substrates.However, devices formed on bulk-semiconductor substrates have moreparasitic capacitance than SOI substrates due to junction capacitance.Furthermore, junction leakage current is a significant concern whenoperating on bulk-semiconductor substrates, as currents can take pathsdeep in the substrate. These concerns apply to both fin FETs and planarFETs.

SUMMARY

A semiconductor device includes a semiconductor layer having a channelregion and source/drain regions. A gate stack is formed on the channelregion. A dielectric layer is formed on the semiconductor layer in thesource/drain regions. Source/drain structures are formed over thedielectric layer in the source/drain regions.

A planar semiconductor device includes a bulk semiconductor substratehaving a channel region and source/drain regions. A gate stack is formedon the channel region of the bulk semiconductor substrate. A dielectriclayer is formed in recesses in the source/drain regions of the bulksemiconductor substrate. Source/drain structures are formed over thedielectric layer in the source/drain regions of the bulk semiconductorsubstrate.

A fin semiconductor device includes a fin formed from a bulksemiconductor substrate. The fin includes a channel region andsource/drain regions. A gate stack is formed on the channel region ofthe fin. A dielectric layer is formed on the source/drain regions of thefin. Source/drain structures are formed over the dielectric layer.

These and other features and advantages will become apparent from thefollowing detailed description of illustrative embodiments thereof,which is to be read in connection with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The following description will provide details of preferred embodimentswith reference to the following figures wherein:

FIG. 1 is a cross-sectional diagram illustrating a step in the formationof a field effect transistor (FET) having dielectric-lined source anddrain regions, where a dummy gate is formed on a semiconductorsubstrate, in accordance with an embodiment of the present invention;

FIG. 2 is a cross-sectional diagram illustrating a step in the formationof a FET having dielectric-lined source and drain regions, whererecesses are formed at sides of the dummy gate, in accordance with anembodiment of the present invention;

FIG. 3 is a cross-sectional diagram illustrating a step in the formationof a FET having dielectric-lined source and drain regions, where asacrificial layer is formed in the recesses, in accordance with anembodiment of the present invention;

FIG. 4 is a cross-sectional diagram illustrating a step in the formationof a FET having dielectric-lined source and drain regions, where areactant layer is formed over the sacrificial layer, in accordance withan embodiment of the present invention;

FIG. 5 is a cross-sectional diagram illustrating a step in the formationof a FET having dielectric-lined source and drain regions, where ananneal is performed to form a dielectric liner, in accordance with anembodiment of the present invention;

FIG. 6 is a cross-sectional diagram illustrating a step in the formationof a FET having dielectric-lined source and drain regions, where sourceand drain regions are formed in the recesses, in accordance with anembodiment of the present invention;

FIG. 7 is a cross-sectional diagram illustrating a step in the formationof a FET having dielectric-lined source and drain regions, wheredielectric structures are formed over the source and drain regions, inaccordance with an embodiment of the present invention;

FIG. 8 is a cross-sectional diagram illustrating a step in the formationof a FET having dielectric-lined source and drain regions, where thedummy gate is replaced with a final gate stack, in accordance with anembodiment of the present invention;

FIG. 9 is a cross-sectional diagram illustrating a step in the formationof a FET having dielectric-lined source and drain regions, where sourceand drain contacts are formed, in accordance with an embodiment of thepresent invention;

FIG. 10 is a block/flow diagram of a method of forming a planar FEThaving dielectric-lined source and drain regions in accordance with anembodiment of the present invention;

FIG. 11 is a cross-sectional diagram illustrating a step in theformation of a FET having dielectric-lined source and drain regions,where a dummy gate is formed on a semiconductor fin, in accordance withan embodiment of the present invention;

FIG. 12 is a cross-sectional diagram illustrating a step in theformation of a FET having dielectric-lined source and drain regions,where source and drain regions of the semiconductor fin are etched back,in accordance with an embodiment of the present invention;

FIG. 13 is a cross-sectional diagram illustrating a step in theformation of a FET having dielectric-lined source and drain regions,where a sacrificial layer is formed on the source and drain regions ofthe semiconductor fin, in accordance with an embodiment of the presentinvention;

FIG. 14 is a cross-sectional diagram illustrating a step in theformation of a FET having dielectric-lined source and drain regions,where a reactant layer is formed over the sacrificial layer, inaccordance with an embodiment of the present invention;

FIG. 15 is a cross-sectional diagram illustrating a step in theformation of a FET having dielectric-lined source and drain regions,where an anneal is performed to form a dielectric liner, in accordancewith an embodiment of the present invention;

FIG. 16 is a cross-sectional diagram illustrating a step in theformation of a FET having dielectric-lined source and drain regions,where source and drain structures are formed on the dielectric liner, inaccordance with an embodiment of the present invention; and

FIG. 17 is a block/flow diagram of a method of forming a fin FET havingdielectric-lined source and drain regions in accordance with anembodiment of the present invention.

DETAILED DESCRIPTION

Embodiments of the present invention use dielectric liners formedbeneath the source/drain regions of field effect transistors (FETs) toreduce junction capacitance and off-state junction leakage currents fromthe source/drain junction. Not only do the dielectric liners preventleakage currents directly, they also prevent out-diffusion of dopantsfrom the source/drain regions that might create new parasitic leakagepaths.

The present embodiments include both fin FETs and planar FETs and bothn-type FETs and p-type FETs. It is specifically contemplated that thedielectric liners may be formed using the reaction of germanium dioxidewith silicon germanium, causing the germanium to be separated out andleaving silicon dioxide behind.

Referring now to FIG. 1, a cross-sectional diagram of a step in theformation of a planar FET is shown. A planar FET is characterized by thetransistor's channel having a conduction path that is within thesubstrate itself. A semiconductor substrate 102 is shown and isspecifically contemplated as being formed from a bulk semiconductormaterial. A dummy gate 104 is formed on the surface of the semiconductorsubstrate, with spacers 106 being formed on sidewalls of the dummy gate104.

In one example, the bulk-semiconductor substrate 102 may be asilicon-containing material. Illustrative examples of silicon-containingmaterials suitable for the bulk-semiconductor substrate include, but arenot limited to, silicon, silicon germanium, silicon germanium carbide,silicon carbide, polysilicon, epitaxial silicon, amorphous silicon, andmulti-layers thereof. Although silicon is the predominantly usedsemiconductor material in wafer fabrication, alternative semiconductormaterials can be employed, such as, but not limited to, germanium,gallium arsenide, gallium nitride, cadmium telluride, and zinc selenide.

It is specifically contemplated that the dummy gate 104 may be formedfrom polycrystalline silicon, though it should be understood that anymaterial having appropriate etch selectivity may be used instead. Thedielectric spacers 106 may be formed from a dielectric material such as,e.g., silicon nitride. As used herein, the term “selective” in referenceto a material removal process denotes that the rate of material removalfor a first material is greater than the rate of removal for at leastanother material of the structure to which the material removal processis being applied. In some embodiments, etch selectivity may denote thatan etch rate of one material under the etch in question is at least tentimes greater than an etch rate for another material under the sameetch.

Referring now to FIG. 2, a cross-sectional diagram of a step in theformation of a planar FET is shown. Source/drain recesses 202 are formedon respective sides of the dummy gate 104. The source/drain recesses 202may, in some embodiments, be formed by a selective anisotropic etchfollowed by a selective wet or dry chemical etch to widen the holecreated by the anisotropic etch. The source/drain recesses 202 thatresult have facets 204 that include a crystalline orientation of, e.g.,<111>, while bottom surfaces 206 have a crystalline orientation of,e.g., <100>. It is specifically contemplated that, for a siliconsubstrate, the second etch may be a dilute hydrofluoric acid etch, apotassium hydroxide etch, or a tetramethyl ammonium hydroxide etc.

Crystalline orientation refers to the ordered arrangement atoms in aparticular crystal structure along a given surface. In one example,silicon forms a “face-centered diamond-cubic” crystal structure, andcutting a silicon crystal along different planes will result indiffering patterns of atoms being presented along the surface that isproduced. These patterns are identified with Miller indices (e.g.,<100>, <111>, etc.), with different Miller indices corresponding todifferent crystalline orientations. Different crystalline orientationswill have different properties during certain processes, such as etchesand epitaxial growth.

The anisotropic etch may include a reactive ion etch (RIE). RIE is aform of plasma etching in which during etching the surface to be etchedis placed on the RF powered electrode. Moreover, during RIE the surfaceto be etched takes on a potential that accelerates the etching speciesextracted from plasma toward the surface, in which the chemical etchingreaction is taking place in the direction normal to the surface. Otherexamples of anisotropic etching that can be used at this point of thepresent invention include ion beam etching, plasma etching or laserablation.

Referring now to FIG. 3, a cross-sectional diagram of a step in theformation of a planar FET is shown. A sacrificial layer 302 isepitaxially grown from bottom surfaces 206 of the source/drain recesses202. It is specifically contemplated that the sacrificial layer 302 willbe formed from silicon germanium, with an exemplary germaniumconcentration range of between about 20% and about 70%, with a specificexemplary concentration of about 40%, though it should be understoodthat other materials and other concentrations may be used instead. Insome embodiments the sacrificial layer will have a thickness betweenabout 4 nm and about 10 nm.

The terms “epitaxial growth” means the growth of a semiconductormaterial on a deposition surface of a semiconductor material, in whichthe semiconductor material being grown has substantially the samecrystalline characteristics as the semiconductor material of thedeposition surface. The term “epitaxial material” denotes a materialthat is formed using epitaxial growth. In some embodiments, when thechemical reactants are controlled and the system parameters setcorrectly, the depositing atoms arrive at the deposition surface withsufficient energy to move around on the surface and orient themselves tothe crystal arrangement of the atoms of the deposition surface. Thus, insome examples, an epitaxial film deposited on a crystal surface having a<100> crystalline orientation will take on a <100> crystallineorientation.

An epitaxial growth process may cause material to grow significantlyfaster on surfaces with a <100> crystalline orientation than on surfaceswith a <111> crystalline orientation. As a result, the bottom surfaces206 of the source/drain recesses 202 will accumulate significantly moresacrificial material than the facets 204. Any material that does grownon the facets 204 can then be removed by a short etch-back that leavesthe majority of the sacrificial material on the bottom surfaces 206intact.

It should be noted that, although these structures are not shown in thepresent figures for the sake of simplicity, the space on substrate'ssurface around the source/drain recesses 202 will have other structures,such as dummy gates, blocking that space. Thus, the epitaxial growthprocess does not reach the top surface of the substrate 102 andadditional material does not grow from the top of the substrate 102.

Referring now to FIG. 4, a cross-sectional diagram of a step in theformation of a planar FET is shown. A reactant layer 402 is depositedover the layer of sacrificial material 302 and other surfaces of thedevice. It is specifically contemplated that the reactant layer 402 maybe formed from, e.g., germanium dioxide and may be deposited by atomiclayer deposition (ALD), but any appropriate deposition process may beused instead, such as chemical vapor deposition (CVD), physical vapordeposition (PVD), or gas-cluster ion beam (GCIB) deposition. Thereactant layer 402 may be deposited with an exemplary thickness rangingbetween about 3 nm and about 10 nm.

CVD is a deposition process in which a deposited species is formed as aresult of chemical reaction between gaseous reactants at greater thanroom temperature (e.g., from about 25° C. about 900° C.). The solidproduct of the reaction is deposited on the surface on which a film,coating, or layer of the solid product is to be formed. Variations ofCVD processes include, but are not limited to, Atmospheric Pressure CVD(APCVD), Low Pressure CVD (LPCVD), Plasma Enhanced CVD (PECVD), andMetal-Organic CVD (MOCVD) and combinations thereof may also be employed.In alternative embodiments that use PVD, a sputtering apparatus mayinclude direct-current diode systems, radio frequency sputtering,magnetron sputtering, or ionized metal plasma sputtering. In alternativeembodiments that use ALD, chemical precursors react with the surface ofa material one at a time to deposit a thin film on the surface. Inalternative embodiments that use GCIB deposition, a high-pressure gas isallowed to expand in a vacuum, subsequently condensing into clusters.The clusters can be ionized and directed onto a surface, providing ahighly anisotropic deposition.

Referring now to FIG. 5, a cross-sectional diagram of a step in theformation of a planar FET is shown. The chemistry of the sacrificiallayer 302 and the reactant layer 402 are selected such that, when ananneal is performed, a reaction between the reactant layer 402 and thesacrificial layer 302 creates a dielectric layer 504. In the specificcase of a silicon germanium sacrificial layer 302 and a germaniumdioxide reactant layer 402, silicon diffuses out of the germaniumdioxide layer 402 and into layer 302, replacing the germanium there toform a layer of pure silicon dioxide 502. The germanium that is freedfrom the germanium dioxide layer 402 is released as gaseous germaniumoxide (GeO). Any unreacted germanium dioxide material from layer 402 maythen be etched away using, e.g., a wash in deionized water.

In one specific embodiment, the anneal may be performed at about 600° C.in a nitrogen gas ambient environment. It should be understood that theanneal temperature is strongly dependent on the composition of thesacrificial layer 302. In embodiments where silicon germanium is usedfor the sacrificial layer 302 and the germanium concentration is in therange between about 20% and about 70%, the anneal may be performed at atemperature in the range between about 750° C. and about 450° C. Toaccelerate the reaction of the reactant layer 402 and the sacrificiallayer 302, a redox has ambient may be used. In the case of germaniumdioxide in the reactant layer 402 and silicon germanium in thesacrificial layer 302, such redox gases may include hydrogen,hydrogen/helium, nitrogen/helium, and argon/helium. A vacuum may also beused.

Referring now to FIG. 6, a cross-sectional diagram of a step in theformation of a planar FET is shown. Source and drain regions 602 areepitaxially grown in the source/drain recesses 202. The source and drainregions 602 are partially isolated from the semiconductor substrate 102by the dielectric regions 504. The source and drain regions 602 may begrown to a height that extends beyond the top surface of thesemiconductor substrate 102.

The source and drain regions 602 may be in situ doped with anappropriate dopant type. As used herein, “p-type” refers to the additionof impurities to an intrinsic semiconductor that creates deficiencies ofvalence electrons. In a silicon-containing substrate, examples of p-typedopants, i.e., impurities, include but are not limited to: boron,aluminum, gallium and indium. As used herein, “n-type” refers to theaddition of impurities that contributes free electrons to an intrinsicsemiconductor in a silicon containing substrate examples of n-typedopants, i.e., impurities, include but are not limited to antimony,arsenic and phosphorous. The dopant type defines the type of transistorthat is created, with n-type dopants being used in the source and drainregions of n-type FETs and with p-type dopants being used in the sourceand drain regions of p-type FETs.

Referring now to FIG. 7, a cross-sectional diagram of a step in theformation of a planar FET is shown. A liner 702 is conformally depositedusing, for example, CVD, PLV, or ALD, and may be formed from anappropriate dielectric material such as, e.g., silicon nitride. Aninter-layer dielectric 704 is then deposited by any appropriate processsuch as, e.g., CVD, PVD, ALD, GCIB deposition, or a spin-on flowableoxide process and may be formed from, e.g., silicon dioxide. Theinter-layer dielectric 704 may then be polished down using, for example,a chemical mechanical planarization (CMP) process that stops on thematerial of the liner 702.

CMP is performed using, e.g., a chemical or granular slurry andmechanical force to gradually remove upper layers of the device. Theslurry may be formulated to be unable to dissolve, for example, thesilicon nitride of the liner 702, resulting in the CMP process'sinability to proceed any farther than that layer.

Referring now to FIG. 8, a cross-sectional diagram of a step in theformation of a planar FET is shown. The dummy gate 104 is removed and agate stack is deposited in its place. The gate stack includes a gatedielectric 802, an optional work function metal 804, and a gateconductor 806.

The gate dielectric 802 may be formed from, e.g., a high-k dielectricmaterial. As used herein, the term “high-k” means a material having adielectric constant that is greater than silicon dioxide at roomtemperature (e.g., about 20° C. to about 25° C.) and atmosphericpressure (e.g., about 1 atm). Examples of high-k dielectric materialsinclude but are not limited to metal oxides such as hafnium oxide,hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide,lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide,zirconium silicon oxynitride, tantalum oxide, titanium oxide, bariumstrontium titanium oxide, barium titanium oxide, strontium titaniumoxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, andlead zinc niobate. The high-k dielectric material may further includedopants such as lanthanum and aluminum.

The work function metal layer 804 may be formed from an n-type or ap-type work function metal, as appropriate to the device being formed.The work function metal layer may be deposited by a PVD process, such assputtering, CVD, or ALD.

As used herein, a “p-type work function metal layer” is a metal layerthat effectuates a p-type threshold voltage shift. In one embodiment,the work function of the p-type work function metal layer ranges from4.9 eV to 5.2 eV. As used herein, “threshold voltage” is the lowestattainable gate voltage that will turn on a semiconductor device, e.g.,transistor, by making the channel of the device conductive. The term“p-type threshold voltage shift” as used herein means a shift in theFermi energy of a p-type semiconductor device towards a valence band ofsilicon in the silicon containing substrate of the p-type semiconductordevice. A “valence band” is the highest range of electron energies whereelectrons are normally present at absolute zero. In one embodiment, ap-type work function metal layer may be formed from titanium nitride,titanium aluminum nitride, ruthenium, platinum, molybdenum, cobalt, andalloys and combinations thereof.

As used herein, an “n-type work function metal layer” is a metal layerthat effectuates an n-type threshold voltage shift. “N-type thresholdvoltage shift” as used herein means a shift in the Fermi energy of ann-type semiconductor device towards a conduction band of silicon in asilicon-containing substrate of the n-type semiconductor device. The“conduction band” is the lowest lying electron energy band of the dopedmaterial that is not completely filled with electrons. In oneembodiment, the work function of the n-type work function metal layerranges from 4.1 eV to 4.3 eV. In one embodiment, the n-type workfunction metal layer is formed from at least one of titanium aluminum,tantalum nitride, titanium nitride, hafnium nitride, hafnium silicon, orcombinations thereof. It should be understood that titanium nitride mayplay the role of an n-type work function metal or a p-type work functionmetal, depending on the conditions of its deposition.

The gate conductor 806 may be formed from any appropriate conductivemetal such as, e.g., tungsten, nickel, titanium, molybdenum, tantalum,copper, platinum, silver, gold, ruthenium, iridium, rhenium, rhodium,and alloys thereof. The gate conductor 806 may alternatively be formedfrom a doped semiconductor material such as, e.g., doped polysilicon.

Referring now to FIG. 9, a cross-sectional diagram of a step in theformation of a planar FET is shown. An anisotropic etch is used to etchholes down through the inter-layer dielectric 704 and the liner 702 toreach the source/drain regions 602. Source/drain contacts 902 are thenformed in the holes, providing electrical connectivity to thesource/drain regions, completing the device.

Referring now to FIG. 10, a method of forming a planar FET is shown.Block 1002 forms a dummy gate 104 on a bulk semiconductor substrate 102.This may be performed by any appropriate patterning process including,e.g., photolithography. Block 1004 etches source and drain recesses 202into the substrate 102 on opposite sides of the dummy gate 104. Theformation of the source and drain recesses 202 may be accomplished usingan initial anisotropic etch, followed by an isotropic etch thatpartially undercuts at least spacers 106.

Block 1006 forms sacrificial layer 302 at the bottom surface 206 of thesource/drain recesses 202. This may be accomplished by epitaxiallygrowing sacrificial material, such as silicon germanium with a germaniumconcentration of about 40%, on the exposed substrate surfaces. Thebottom surface 206 of the recesses 202 may have a crystallineorientation that promotes faster growth than the facets 204 (e.g.,having an orientation of <100> versus <111>), and an isotropic etch isthen used to remove the relatively small amount of sacrificial materialfrom the facets 204.

Block 1008 forms a reactant layer 402 on the sacrificial layer 302 byany appropriate deposition process. The reactant layer may be formedfrom, e.g., germanium dioxide. Block 1010 performs an anneal to formdielectric layer 504. The anneal drives silicon from the sacrificiallayer 302 into the reactant layer 402 where it replaces the germanium toform dielectric layer 504. The germanium released from the reactantlayer 402 escapes as gaseous germanium oxide. Block 1012 then washesaway the remaining reactant layer which, in the case of germaniumdioxide, is water-soluble.

Block 1014 then epitaxially grows source/drain regions 602 on thedielectric layer 504. The source/drain regions 602 may be in situ dopedand may be formed from any appropriate semiconductor material such as,e.g., doped silicon. Block 1016 forms liner 702 and inter-layerdielectric over the source/drain regions 602 and the dummy gate 104.Block 1020 then forms the source/drain contacts 902 to complete thetransistor device.

Referring now to FIG. 11, a cross-sectional diagram of a step in theformation of a fin FET is shown. As with the planar FET step shown inFIG. 1, a dummy gate 1104 and dummy gate spacers 1106 are formed over abulk semiconductor substrate 1102. In this case, however, a fin 1108 isformed from the substrate 1102. The fin 1108 may be formed by, e.g., ananisotropic etch such as RIE or any of the other anisotropic processesdescribed above, and may be separated from other structures by ashallow-trench isolation that deposits dielectric material between suchstructures. In this and subsequent views, the cross-section is shown asbeing parallel with the fin's length, with the fin 1108 having arelatively narrow width in the direction perpendicular to the page. Adashed line illustrates for this figure where the base of the fin 1108is relative to the bulk substrate 1102. It should be understood that,where not otherwise specified, the processes, materials, and structuresused in the formation of the fin FET may be the same as those describedabove with respect to the formation of planar FETs.

Referring now to FIG. 12, a cross-sectional diagram of a step in theformation of a fin FET is shown. The fin 1108 is etched partially downusing the dummy gate 1104 and spacer 1106 as a mask. It is specificallycontemplated that the fin 1108 may be etched down to a point that issomewhat below the top surface of the shallow-trench isolationstructures, but it should be understood that any appropriate fin heightmay be used. The etch leaves behind a channel region 1202 underneath thedummy gate 1104.

Referring now to FIG. 13, a cross-sectional diagram of a step in theformation of a fin FET is shown. A layer of sacrificial material 1302 isformed by epitaxial growth and may be formed from, e.g., silicongermanium having a germanium concentration of about 40%.

Referring now to FIG. 14, a cross-sectional diagram of a step in theformation of a fin FET is shown. A reactant layer 1402 is deposited overthe sacrificial layer 1302 by any appropriate deposition process and maybe formed from, e.g., germanium dioxide.

Referring now to FIG. 15, a cross-sectional diagram of a step in theformation of a fin FET is shown. An anneal is performed that causes thereactant layer 1402 to react with the sacrificial layer 1302 to formdielectric layer 1504 and depleted sacrificial layer 1502. Thedielectric layer 1504 may thus be formed from pure silicon dioxide andthe depleted sacrificial layer may have a germanium concentration ofabout 60%. Unreacted remnants of the reactant layer 1402 may be washedaway using, in the case of germanium dioxide, deionized water or anyother suitable process.

Referring now to FIG. 16, a cross-sectional diagram of a step in theformation of a fin FET is shown. Source and drain regions 1602 areepitaxially grown over the dielectric layer 1504, which insulates thesource and drain regions 1602 from the bulk substrate 1102. Afterformation of the source/drain regions, an appropriate inter-layerdielectric and source/drain contacts (not shown) may also be formed tocomplete the device.

Referring now to FIG. 17, a method of forming a fin FET is shown. Block1702 forms a fin 1108 in a bulk substrate 1702 using any appropriateprocess including, e.g., photolithography with an anisotropic etch orsidewall image transfer. Block 1704 then forms dummy gate 1104 andspacers 1106 over the channel region 1202 of the fin 1108 and block 1706etches the fin 1108 down in source and drain regions around the dummygate 1104.

Block 1708 forms sacrificial layer 1302 on the source and drain regionsof the etched fin, with a particular embodiment epitaxially growingsilicon germanium at a germanium concentration of about 40% for thesacrificial layer 1302. Block 1710 deposits the reactant layer 1402 overthe sacrificial layer 1710, where the reactant layer may be formed fromgermanium dioxide. As in the planar FET embodiment, block 1712 performsan anneal at, e.g., about 600° C. in a gaseous nitrogen environment toform dielectric layer 1502.

Block 1714 grows source/drain regions 1602 using an in situ dopedepitaxial growth process. Block 1716 then forms an inter-layerdielectric (not shown) over and around the fin and source/drain regions,which may include a deposition of the inter-layer dielectric materialand a CMP process down to the level of the dummy gate 1104. Block 1718then replaces the dummy gate 1104 with a gate stack (not shown),including a gate dielectric, an optional work function metal, and a gateconductor. Block 1720 forms source/drain contacts (not shown) by etchingholes through the inter-layer dielectric and depositing an appropriateconductive contact material.

It is to be understood that aspects of the present invention will bedescribed in terms of a given illustrative architecture; however, otherarchitectures, structures, substrate materials and process features andsteps can be varied within the scope of aspects of the presentinvention.

It will also be understood that when an element such as a layer, regionor substrate is referred to as being “on” or “over” another element, itcan be directly on the other element or intervening elements can also bepresent. In contrast, when an element is referred to as being “directlyon” or “directly over” another element, there are no interveningelements present. It will also be understood that when an element isreferred to as being “connected” or “coupled” to another element, it canbe directly connected or coupled to the other element or interveningelements can be present. In contrast, when an element is referred to asbeing “directly connected” or “directly coupled” to another element,there are no intervening elements present.

The present embodiments can include a design for an integrated circuitchip, which can be created in a graphical computer programming language,and stored in a computer storage medium (such as a disk, tape, physicalhard drive, or virtual hard drive such as in a storage access network).If the designer does not fabricate chips or the photolithographic masksused to fabricate chips, the designer can transmit the resulting designby physical means (e.g., by providing a copy of the storage mediumstoring the design) or electronically (e.g., through the Internet) tosuch entities, directly or indirectly. The stored design is thenconverted into the appropriate format (e.g., GDSII) for the fabricationof photolithographic masks, which typically include multiple copies ofthe chip design in question that are to be formed on a wafer. Thephotolithographic masks are utilized to define areas of the wafer(and/or the layers thereon) to be etched or otherwise processed.

Methods as described herein can be used in the fabrication of integratedcircuit chips. The resulting integrated circuit chips can be distributedby the fabricator in raw wafer form (that is, as a single wafer that hasmultiple unpackaged chips), as a bare die, or in a packaged form. In thelatter case, the chip is mounted in a single chip package (such as aplastic carrier, with leads that are affixed to a motherboard or otherhigher level carrier) or in a multichip package (such as a ceramiccarrier that has either or both surface interconnections or buriedinterconnections). In any case, the chip is then integrated with otherchips, discrete circuit elements, and/or other signal processing devicesas part of either (a) an intermediate product, such as a motherboard, or(b) an end product. The end product can be any product that includesintegrated circuit chips, ranging from toys and other low-endapplications to advanced computer products having a display, a keyboardor other input device, and a central processor.

It should also be understood that material compounds will be describedin terms of listed elements, e.g., SiGe. These compounds includedifferent proportions of the elements within the compound, e.g., SiGeincludes Si_(x)Ge_(1-x) where x is less than or equal to 1, etc. Inaddition, other elements can be included in the compound and stillfunction in accordance with the present principles. The compounds withadditional elements will be referred to herein as alloys.

Reference in the specification to “one embodiment” or “an embodiment”,as well as other variations thereof, means that a particular feature,structure, characteristic, and so forth described in connection with theembodiment is included in at least one embodiment. Thus, the appearancesof the phrase “in one embodiment” or “in an embodiment”, as well anyother variations, appearing in various places throughout thespecification are not necessarily all referring to the same embodiment.

It is to be appreciated that the use of any of the following “/”,“and/or”, and “at least one of”, for example, in the cases of “A/B”, “Aand/or B” and “at least one of A and B”, is intended to encompass theselection of the first listed option (A) only, or the selection of thesecond listed option (B) only, or the selection of both options (A andB). As a further example, in the cases of “A, B, and/or C” and “at leastone of A, B, and C”, such phrasing is intended to encompass theselection of the first listed option (A) only, or the selection of thesecond listed option (B) only, or the selection of the third listedoption (C) only, or the selection of the first and the second listedoptions (A and B) only, or the selection of the first and third listedoptions (A and C) only, or the selection of the second and third listedoptions (B and C) only, or the selection of all three options (A and Band C). This can be extended, as readily apparent by one of ordinaryskill in this and related arts, for as many items listed.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of exampleembodiments. As used herein, the singular forms “a,” “an” and “the” areintended to include the plural forms as well, unless the context clearlyindicates otherwise. It will be further understood that the terms“comprises,” “comprising,” “includes” and/or “including,” when usedherein, specify the presence of stated features, integers, steps,operations, elements and/or components, but do not preclude the presenceor addition of one or more other features, integers, steps, operations,elements, components and/or groups thereof.

Spatially relative terms, such as “beneath,” “below,” “lower,” “above,”“upper,” and the like, can be used herein for ease of description todescribe one element's or feature's relationship to another element(s)or feature(s) as illustrated in the FIGS. it will be understood that thespatially relative terms are intended to encompass differentorientations of the device in use or operation in addition to theorientation depicted in the FIGS. For example, if the device in theFIGS. is to over, elements described as “below” or “beneath” otherelements or features would then be oriented “above” the other elementsor features. Thus, the term “below” can encompass both an orientation ofabove and below. The device can be otherwise oriented (rotated 90degrees or at other orientations), and the spatially relativedescriptors used herein can be interpreted accordingly. In addition, itwill also be understood that when a layer is referred to as being“between” two layers, it can be the only layer between the two layers,or one or more intervening layers can also be present.

It will be understood that, although the terms first, second, etc. canbe used herein to describe various elements, these elements should notbe limited by these terms. These terms are only used to distinguish oneelement from another element. Thus, a first element discussed belowcould be termed a second element without departing from the scope of thepresent concept.

Having described preferred embodiments of transistors withdielectric-isolated source and drain regions (which are intended to beillustrative and not limiting), it is noted that modifications andvariations can be made by persons skilled in the art in light of theabove teachings. It is therefore to be understood that changes may bemade in the particular embodiments disclosed which are within the scopeof the invention as outlined by the appended claims. Having thusdescribed aspects of the invention, with the details and particularityrequired by the patent laws, what is claimed and desired protected byLetters Patent is set forth in the appended claims.

What is claimed is:
 1. A semiconductor device, comprising: asemiconductor layer comprising a channel region and source/drainregions; a gate stack formed on the channel region; a dielectric layerformed on the semiconductor layer in the source/drain regions; andsource/drain structures formed over the dielectric layer in thesource/drain regions.
 2. The semiconductor device of claim 1, furthercomprising a layer of sacrificial material below the dielectric layer inthe recesses.
 3. The semiconductor device of claim 2, wherein thedielectric layer is formed from silicon dioxide and the sacrificiallayer is formed from silicon germanium.
 4. The semiconductor device ofclaim 1, wherein a surface of the semiconductor layer has a crystallineorientation of <100>.
 5. The semiconductor device of claim 1, whereinthe channel region of the fin has a height greater than the source/drainregions of the fin.
 6. The semiconductor device of claim 5, wherein ashallow-trench isolation dielectric comes to a height greater than theheight of the source/drain regions of the fin.
 7. The semiconductordevice of claim 1, wherein the source/drain structures are epitaxiallygrown semiconductor structures.
 8. The semiconductor device of claim 1,wherein the source/drain structures have a trapezoidal cross-section. 9.The semiconductor device of claim 1, wherein a bottom surface of thesource/drain structures has a height lower than a top surface of thesemiconductor layer.
 10. A planar semiconductor device, comprising: abulk semiconductor substrate comprising a channel region andsource/drain regions; a gate stack formed on the channel region of thebulk semiconductor substrate; a dielectric layer formed in recesses inthe source/drain regions of the bulk semiconductor substrate; andsource/drain structures formed over the dielectric layer in thesource/drain regions of the bulk semiconductor substrate.
 11. Thesemiconductor device of claim 10, further comprising a layer ofsacrificial material below the dielectric layer in the recesses.
 12. Thesemiconductor device of claim 11, wherein the dielectric layer is formedfrom silicon dioxide and the sacrificial layer is formed from silicongermanium.
 13. The semiconductor device of claim 10, wherein a bottomsurface of the recesses has a crystalline orientation of <100> andwherein other facets of the recesses have a crystalline orientation of<111>.
 14. The semiconductor device of claim 10, wherein thesource/drain structures have a trapezoidal cross-section.
 15. Thesemiconductor device of claim 10, wherein a bottom surface of thesource/drain structures has a height lower than a top surface of thebulk semiconductor substrate.
 16. A fin semiconductor device,comprising: a fin formed from a bulk semiconductor substrate, comprisinga channel region and source/drain regions; a gate stack formed on thechannel region of the fin; a dielectric layer formed on the source/drainregions of the fin; and source/drain structures formed over thedielectric layer.
 17. The semiconductor device of claim 16, furthercomprising a layer of sacrificial material between the dielectric layerand the fin.
 18. The semiconductor device of claim 17, wherein thedielectric layer is formed from silicon dioxide and the sacrificiallayer is formed from silicon germanium.
 19. The semiconductor device ofclaim 16, wherein the channel region of the fin has a height greaterthan the source/drain regions of the fin.
 20. The semiconductor deviceof claim 19, wherein a shallow-trench isolation dielectric comes to aheight greater than the height of the source/drain regions of the fin.